The role of power integrity is increasingly important, as products increase in the fringes to higher current draw, longer battery life and higher noise sensitivity. In this year's High Speed Symposium, we pull together four industry experts on power integrity to offer a perspective on some of these challenges in designing, building and measuring products at the edge.
The symposium consists of four presentations followed by a panel discussion with each of the speakers participating, led by the editor of the Signal Integrity Journal, Eric Bogatin. The theme for this year's panel will be "Putting Power Integrity in Perspective: How do we know when to apply what guidelines to what types of systems.”
Eric Bogatin is currently the editor of the Signal Integrity Journal, an Adjunct Professor at the University of Colorado - Boulder in the ECEE dept, a Signal Integrity Evangelist with Teledyne LeCroy, and Dean of the Teledyne LeCroy Signal Integrity Academy. Bogatin received his BS in physics from MIT and MS and PhD in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft and Interconnect Devices. He has written six technical books in the field and presented classes and lectures on signal integrity worldwide.
PDN Power Integrity
Linear Voltage Regulator Model (VRM) for Power Integrity Simulations
A linear voltage regulator model (VRM) is necessary to enable power integrity (PI) simulations at frequencies beyond the VRM bandwidth. A power integrity engineer is often interested in the properties of the board power planes and vias, the package balls, vias, power planes and package caps, and the die bumps, on-die power grid and on-die capacitance for the silicon load. These power integrity components are particularly important in the 1 MHz to 500 MHz frequency band. This presentation takes a deep-dive look at a VRM model with a few simple linear components to address these needs.
Many people in the industry are somewhat confused about the meaning and definitions of target impedance and actual PDN impedance. This paper will address these issues. PDN design is a matter of managing risk, cost and performance. Target impedance is not a law, it a reference line that is useful for cost-effective and robust PDN design. Attendees will learn about the relationship between PDN impedance and target impedance and receive guidance on how to calculate target impedance.
Larry Smith is a principal power integrity engineer presently associated with PDNpowerIntegrity.com. He has worked for Qualcomm, Altera, Sun Microsystems and IBM in various signal and power integrity roles. He and Eric Bogatin have a book on Principles of Power Integrity for PDN Design published in 2017.
100uΩ Probing Methods
Measuring DC resistance lower than 100uΩ is trivial using the 4-wire method. Measuring AC impedance in this range using the two-port shunt-through method becomes increasingly difficult as frequencies increase. The location and position of the probes relative to each other is very important, as is the parasitic inductance of each probe. Different calibration methods can be used to partially compensate for these sources of measurement error. Simulations can also be adjusted to mimic the exact probing method used on the DUT. These techniques allow accurate measurements in the 100uΩ range to at least 10MHz.
Brian Hosteler is an electrical engineer for Cray, Inc. He is currently responsible for the power integrity of new printed circuit board designs. He is also responsible for the power integrity of the power distribution network in multi-cabinet supercomputer systems. He has a background in test engineering for defense electronics and design experience with various consumer electronics, including wireless sensors. He holds a BS from Indiana State University and a BS from Purdue University.
Designing and measuring 100uOhm Power Rails
There are many challenges related to 100uOhm power rail design. The VRM options are very limited, the measurements are challenging even the best instruments and everything matters. Simulation and measurement comparisons become much more difficult and the number of decoupling capacitors increases exponentially. With operating currents approaching 750 Amps, load testers present yet another new challenge. The switching power supply ripple is a much larger percentage of the noise budget, and this makes achieving a reasonable signal to noise ratio interesting to say the least. In this presentation I'll discuss the many challenges associated with this "new normal" for high power rails and I'll provide a few tips for success.
Steve Sandler has been involved with power system engineering for nearly 40 years. The founder and CEO of Picotest.com, a company specializing in instruments and accessories for high-performance power system and distributed system testing, Steve is also the founder of AEi Systems, a company that specializes in worst-case circuit analysis for high-reliability industries.
He frequently lectures and publishes internationally on the topics of power integrity and distributed power system design. His most recent books include: Switched-Mode Power Supply Simulation with SPICE (2018) and Power Integrity: Measuring, Optimizing and Troubleshooting Power-Related Parameters in Electronics Systems (2014). Steve is a winner of the Jim Williams ACE Award for Contributor of the Year (2015) and the recipient of both the DesignCon 2017 and EDICON USA 2017 Best Paper Awards.